參數(shù)資料
| 型號： | EP4S100G3F45I2 |
| 廠商： | Altera |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 290K 1932FBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 11648 |
| 邏輯元件/單元數(shù)： | 291200 |
| RAM 位總計： | 17661952 |
| 輸入/輸出數(shù)： | 781 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1932-BBGA |
| 供應商設備封裝： | 1932-FBGA（45x45） |
1–4
Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
September 2012
Altera Corporation
Stratix IV E Device
Stratix IV E devices provide an excellent solution for applications that do not require
high-speed CDR-based transceivers, but are logic, user I/O, or memory intensive.
Figure 1–2 shows a high-level Stratix IV E chip view.
Figure 1–2. Stratix IV E Chip View (1)
Note to Figure 1–2:
(1) Resource counts vary with device selection, package selection, or both.
General Purpose
I/O and Memory
Interface
General Purpose I/O and
150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
General Purpose
I/O and Memory
Interface
PLL
General Purpose
I/O and Memory
Interface
General Purpose
I/O and Memory
Interface
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
General Purpose I/O and
High-Speed LVDS I/O with DPA
and Soft-CDR
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
General
Purpose
I/O and
High-Speed
LVDS I/O
with DPA
and Soft-CDR
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S100G3F45I2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G3F45I3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G3F45I3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 11648 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G4F45I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G4F45I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 14144 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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