- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4481 > EP4CGX22CF19I7N (Altera)IC CYCLONE IV GX FPGA 22K 324FBG PDF資料下載
參數(shù)資料
| 型號(hào)： | EP4CGX22CF19I7N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 33/42頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CYCLONE IV GX FPGA 22K 324FBG |
| 產(chǎn)品培訓(xùn)模塊： | Cyclone IV FPGA Family Overview |
| 特色產(chǎn)品： | Cyclone? IV FPGAs |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | CYCLONE® IV GX |
| LAB/CLB數(shù)： | 1330 |
| 邏輯元件/單元數(shù)： | 21280 |
| RAM 位總計(jì)： | 774144 |
| 輸入/輸出數(shù)： | 150 |
| 電源電壓： | 1.16 V ~ 1.24 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 324-LBGA |
| 供應(yīng)商設(shè)備封裝： | 324-FBGA（19x19） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)
Chapter 1: Cyclone IV Device Datasheet
1–39
Glossary
December 2013
Altera Corporation
R
RL
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver Input
Waveform
Receiver input waveform for LVDS and LVPECL differential standards:
Receiver input
skew margin
(RSKM)
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
S
Single-ended
voltage-
referenced I/O
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Table 1–46. Glossary (Part 3 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
0 V
V
CM
p
- n
V
ID
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP4CGX22CF19C6N | IC CYCLONE IV GX FPGA 22K 324FBG |
| A3P1000-FG484 | IC FPGA 1KB FLASH 1M 484-FBGA |
| M1A3P1000-FG484 | IC FPGA M1 1KB FLASH 1M 484FBGA |
| M1A3P1000-FGG484 | IC FPGA M1 1KB FLASH 1M 484FBGA |
| APA075-FGG144I | IC FPGA PROASIC+ 75K 144-FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4CGX22F17C8 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX22F23C8N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CGX22F23I7N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX30 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
| EP4CGX30BF14C6 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV GX 1840 LABs 72 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。