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鍨嬭櫉(h脿o)锛� EP4CE75F23C8L
寤犲晢锛� Altera
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 33/42闋�(y猫)
鏂囦欢澶у皬锛� 0K
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鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
鐗硅壊鐢�(ch菐n)鍝侊細 Cyclone? IV FPGAs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� CYCLONE® IV E
LAB/CLB鏁�(sh霉)锛� 4713
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 75408
RAM 浣嶇附瑷�(j矛)锛� 2810880
杓稿叆/杓稿嚭鏁�(sh霉)锛� 292
闆绘簮闆诲锛� 0.97 V ~ 1.03 V
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宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FBGA锛�23x23锛�
Chapter 1: Cyclone IV Device Datasheet
1鈥�39
Glossary
December 2013
Altera Corporation
R
RL
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver Input
Waveform
Receiver input waveform for LVDS and LVPECL differential standards:
Receiver input
skew margin
(RSKM)
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI 鈥� SW 鈥� TCCS) / 2.
S
Single-ended
voltage-
referenced I/O
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Table 1鈥�46. Glossary (Part 3 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
0 V
V
CM
p
- n
V
ID
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ACM36DTBD-S664 CONN EDGECARD 72POS R/A .156
EP4CE75F23C7 IC CYCLONE IV FPGA 75K 484FBGA
AX500-1FG676I IC FPGA AXCELERATOR 500K 676FBGA
ACM36DTBN-S664 CONN EDGECARD 72POS R/A .156
AX500-1FGG676I IC FPGA AXCELERATOR 500K 676FBGA
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鍙冩暩(sh霉)鎻忚堪
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