R" />
鍙冩暩璩囨枡
鍨嬭櫉锛� EP4CE30F23C6N
寤犲晢锛� Altera
鏂囦欢闋佹暩锛� 33/42闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC CYCLONE IV FPGA 30K 484FBGA
鐢㈠搧鍩硅〒妯″锛� Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
鐗硅壊鐢㈠搧锛� Cyclone? IV FPGAs
妯欐簴鍖呰锛� 60
绯诲垪锛� CYCLONE® IV E
LAB/CLB鏁革細 1803
閭忚集鍏冧欢/鍠厓鏁革細 28848
RAM 浣嶇附瑷堬細 608256
杓稿叆/杓稿嚭鏁革細 328
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 484-FBGA锛�23x23锛�
Chapter 1: Cyclone IV Device Datasheet
1鈥�39
Glossary
December 2013
Altera Corporation
R
RL
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver Input
Waveform
Receiver input waveform for LVDS and LVPECL differential standards:
Receiver input
skew margin
(RSKM)
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI 鈥� SW 鈥� TCCS) / 2.
S
Single-ended
voltage-
referenced I/O
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Table 1鈥�46. Glossary (Part 3 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
0 V
V
CM
p
- n
V
ID
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
鐩搁棞PDF璩囨枡
PDF鎻忚堪
GCB70DHBR CONN EDGECARD 140PS R/A .050 SLD
ACM40DRMI-S288 CONN EDGECARD EXTEND 80POS 0.156
AMM22DTKI CONN EDGECARD 44POS DIP .156 SLD
RMM44DRKN-S13 CONN EDGECARD 88POS .156 EXTEND
M1A3P1000-1FGG144 IC FPGA M1 1KB FLASH 1M 144FBGA
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�
鍙冩暩鎻忚堪
EP4CE30F23C7 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄ｅ垪 FPGA - Cyclone IV E 1803 LABs 328 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP4CE30F23C7N 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄ｅ垪 FPGA - Cyclone IV E 1803 LABs 328 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP4CE30F23C8 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄ｅ垪 FPGA - Cyclone IV E 1803 LABs 328 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP4CE30F23C8L 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄ｅ垪 FPGA - Cyclone IV E 1803 LABs 328 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP4CE30F23C8LN 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄ｅ垪 FPGA - Cyclone IV E 1803 LABs 328 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
鐧�(f膩)甯冪穵鎬ラ噰璩硷紝3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫插叆鎴戠殑鍚庤嚭锛屾煡鐪嬪牨鍍�

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩笺€備篃鍙互閫插叆鎴戠殑鍚庤嚭锛屾煡鐪嬪牨鍍�

*鍨嬭櫉 *鏁搁噺 寤犲晢 鎵硅櫉 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱郴鏂瑰紡

*
*
*
    • 鎴�
    • 閲囪喘
    • 鎼滅储
    • 浼氬憳