鍨嬭櫉(h脿o)锛� | EP4CE10F17C6N |
寤�(ch菐ng)鍟嗭細 | Altera |
鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 33/42闋�(y猫) |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC CYCLONE IV FPGA 10K 256FBGA |
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
鐗硅壊鐢�(ch菐n)鍝侊細 | Cyclone? IV FPGAs |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
绯诲垪锛� | CYCLONE® IV E |
LAB/CLB鏁�(sh霉)锛� | 645 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 10320 |
RAM 浣嶇附瑷�(j矛)锛� | 423936 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 179 |
闆绘簮闆诲锛� | 1.15 V ~ 1.25 V |
瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 85°C |
灏佽/澶栨锛� | 256-BGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FBGA锛�17x17锛� |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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M1A3P400-2PQ208 | IC FPGA 1KB FLASH 400K 208-PQFP |
A3P400-2PQ208 | IC FPGA 1KB FLASH 400K 208-PQFP |
AMC28DRXS | CONN EDGECARD 56POS .100 DIP SLD |
A3P250L-FG144I | IC FPGA 1KB FLASH 250K 144-FBGA |
ACM43DTKN-S288 | CONN EDGECARD EXTEND 86POS 0.156 |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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EP4CE10F17C7 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP4CE10F17C7N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP4CE10F17C8 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP4CE10F17C8L | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP4CE10F17C8LN | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪 FPGA - Cyclone IV E 645 LABs 179 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |