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參數(shù)資料
| 型號(hào)： | EP2SGX60EF1152C5N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 1442/1486頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II GX 60K 1152-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 8 |
| 系列： | Stratix® II GX |
| LAB/CLB數(shù)： | 3022 |
| 邏輯元件/單元數(shù)： | 60440 |
| RAM 位總計(jì)： | 2544192 |
| 輸入/輸出數(shù)： | 534 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1152-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1152-FBGA（27x27） |
| 其它名稱： | 544-2185 |
Altera Corporation
4–221
October 2007
Stratix II GX Device Handbook, Volume 2
Stratix II GX ALT2GXB Megafunction User Guide
Table 4–80 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 4–80. MegaWizard Plug-In Manager Options (Page 5 for Serial RapidIO Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Enable static equalizer control This option enables the static equalizer settings. If the
equalizer settings are not changed through the
dynamic reconfiguration controller, the equalizer
remains configured to these static settings. Enabling
the equalizer control enables the equalizer DC gain
option. This DC gain option can be used in conjunction
with equalizer controls and has three legal settings.
Receiver Buffer section
in the Stratix II GX
chapter in volume 2 of
the Stratix II GX Device
Handbook.
What is the Receiver
Common Mode Voltage (RX
VCM)?
The receiver common mode voltage is programmable
between 0.85 V and 1.2 V.
Receiver Buffer section
in the Stratix II GX
chapter in volume 2 of
the Stratix II GX Device
Handbook.
Force signal detection
This option is available only in PIPE mode.
Receiver Buffer Section
in the Stratix II GX
chapter in volume 2 of
the Stratix II GX Device
Handbook.
What is the signal detect and
signal loss threshold?
Use this option when the forced signal detection
option is off and to set the trip point of the signal detect
circuit. This option is available only in PIPE mode.
Receiver Buffer section
in the Stratix II GX
chapter in volume 2 of
the Stratix II GX Device
Handbook.
Use external receiver
termination
This option is available if you want to use an external
termination resistor instead of the on-chip termination
(OCT). If checked, this option turns off the receiver
OCT.
Receiver Buffer section
in the Stratix II GX
chapter in volume 2 of
the Stratix II GX Device
Handbook.
What is the receiver
termination resistance?
This option selects the receiver termination value. The
settings allowed are 100
Ω, 120 Ω, and 150 Ω .
Receiver Buffer section
in the Stratix II GX
chapter in volume 2 of
the Stratix II GX Device
Handbook.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2SGX60EF1152I4 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II GX 3022 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX60EF1152I4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II GX 3022 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX90 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Package Information Datasheet for Mature Altera Devices |
| EP2SGX90E | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix II GX Device |
| EP2SGX90EF1152C3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II GX 4548 LABs 558 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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