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參數(shù)資料
| 型號： | EP2SGX60DF780C5N |
| 廠商： | Altera |
| 文件頁數(shù)： | 212/1486頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II GX 60K 780-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 系列： | Stratix® II GX |
| LAB/CLB數(shù)： | 3022 |
| 邏輯元件/單元數(shù)： | 60440 |
| RAM 位總計(jì)： | 2544192 |
| 輸入/輸出數(shù)： | 364 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 780-BBGA |
| 供應(yīng)商設(shè)備封裝： | 780-FBGA（29x29） |
| 其它名稱： | 544-1762 |
Altera Corporation
10–1
October 2007
10. Selectable I/O Standards
in Stratix II and Stratix II GX
Devices
Introduction
This chapter provides guidelines for using industry I/O standards in
Stratix II and Stratix II GX devices, including:
■
I/O features
■
I/O standards
■
External memory interfaces
■
I/O banks
■
Design considerations
Stratix II and
Stratix II GX I/O
Features
Stratix II and the Stratix II GX devices contain an abundance of adaptive
logic modules (ALMs), embedded memory, high-bandwidth digital
signal processing (DSP) blocks, and extensive routing resources, all of
which can operate at very high core speed.
Stratix II and Stratix II GX devices I/O structure is designed to ensure
that these internal capabilities are fully utilized. There are numerous I/O
features to assist in high-speed data transfer into and out of the device
including:
■
Single-ended, non-voltage-referenced and voltage-referenced I/O
standards
■
High-speed differential I/O standards featuring
serializer/deserializer (SERDES), dynamic phase alignment (DPA),
capable of 1 gigabit per second (Gbps) performance for low-voltage
differential signaling (LVDS), Hypertransport technology, HSTL,
SSTL, and LVPECL
1
HSTL and SSTL I/O standards are used only for PLL clock
inputs and outputs in differential mode. LVPECL is
supported on clock input and outputs of the top and bottom
I/O banks.
■
Double data rate (DDR) I/O pins
■
Programmable output drive strength for voltage-referenced and
non-voltage-referenced single-ended I/O standards
■
Programmable bus-hold
■
Programmable pull-up resistor
■
Open-drain output
■
On-chip series termination
■
On-chip parallel termination
SII52004-4.6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2SGX60DF780I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 3022 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX60DF780I4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 3022 LABs 364 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX60E | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix II GX Device |
| EP2SGX60EF1152C3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 3022 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX60EF1152C3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 3022 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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