
15–4
Altera Corporation
Stratix II GX Device Handbook, Volume 2
October 2007
IEEE Std. 1149.1 Boundary-Scan Register
Figure 15–2 shows a functional model of the IEEE Std. 1149.1 circuitry.
Figure 15–2. IEEE Std. 1149.1 Circuitry
(1)
Refer to the appropriate device data sheet for register lengths.
IEEE Std. 1149.1 boundary-scan testing is controlled by a test access port
(TAP) controller. For more information on the TAP controller, refer to
pins operate the TAP controller, and the TDI and TDO pins provide the
serial path for the data registers. The TDI pin also provides data to the
instruction register, which then generates control logic for the data
registers.
IEEE Std. 1149.1
Boundary-Scan
Register
The boundary-scan register is a large serial shift register that uses the TDI
pin as an input and the TDO pin as an output. The boundary-scan register
consists of 3-bit peripheral elements that are associated with Stratix II or
Stratix II GX I/O pins. You can use the boundary-scan register to test
external pin connections or to capture internal data.
a
UPDATEIR
CLOCKIR
SHIFTIR
UPDATEDR
CLOCKDR
SHIFTDR
TDI
Instruction Register
Bypass Register
Boundary-Scan Register
Instruction Decode
TMS
TCLK
TAP
Controller
ICR Registers
TDO
Data Registers
Device ID Register
TRST (1)
(1)