
Altera Corporation
9–17
October 2007
Stratix II GX Device Handbook, Volume 2
External Memory Interfaces in Stratix II and Stratix II GX Devices
1
To support the RLDRAM II QVLD pin, some of the unused ×4
DQS pins, whose DQ pins were combined to make the bigger
×8/×9, ×16/×18, or ×32/×36 groups, are listed as DQVLD pins
in the Stratix II or Stratix II GX pin table. DQVLD pins are for
input-only operations. The signal coming into this pin can be
captured by the shifted DQS signal like any of the DQ pins.
Table 9–5. Stratix II GX DQS and DQ Bus Mode Support
Device
Package
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
×16/×18 Groups
Number of
×32/×36 Groups
EP2SGX30C
EP2SGX30D
780-pin FineLine BGA
18
8
4
0
EP2SGX60C
EP2SGX60D
780-pin FineLine BGA
18
8
4
0
EP2SGX60E
1,152-pin FineLine BGA
36
18
8
4
EP2SGX90E
1,152-pin FineLine BGA
36
18
8
4
EP2SGX90F
1,508-pin FineLine BGA
36
18
8
4
EP2SGX130G
1,508-pin FineLine BGA
36
18
8
4
(1)
Check the pin table for each DQS/DQ group in the different modes.
Table 9–6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1) Device
Package
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
×16/×18 Groups
Number of
×32/×36 Groups
EP2SGX30
780-pin FineLine BGA
18
8
4
2
EP2SGX60
780-pin FineLine BGA
18
8
4
2
1,152-pin FineLine BGA
25
13
6
3
EP2SGX90
1,152-pin FineLine BGA
25
13
6
3
1,508-pin FineLine BGA
25
12
6
3
EP2SGX130
1,508-pin FineLine BGA
25
12
6
3
(1)
Check the pin table for each DQS/DQ group in the different modes.