
Altera Corporation
3–69
October 2007
Stratix II GX Device Handbook, Volume 2
Stratix II GX Dynamic Reconfiguration
Overall Design Flow for Channel Reconfiguration
The following describes the design flow for Stratix II GX channel
reconfiguration.
ALT2GXB Instantiation
1.
Create an ALT2GXB MegaWizard instantiation. Select the protocol
mode, single width, double width, data rate, and input reference
clock frequency.
2.
Select the required status signals.
3.
In the Reconfig tab, select the channel internals.
1
If you intend to perform only rate division control, proceed to
4.
If you would like to switch between two configurations that have
different input clock frequencies, select the Use alternate reference
clock
option to configure the second TX PLL. Specify the What is
the logical reference clock index?
option value.
5.
If the configuration requires different PLD interface widths or
additional control signals provided in the Reconfig2 tab, select the
Channel interface
option.
6.
Select the appropriate clocking scheme in the Reconfig2 tab.
7.
Select the required additional control signals for the configuration in
the Reconfig2 tab (this is only enabled if the Channel interface
option is selected).
MIF Generation:
8.
Create a top-level design and connect the clock inputs in the
RTL/schematic. Specifically, for the transceiver clock inputs,
connect pll_inclk and rx_cruclk to the input pins that provide
the clock for the protocol mode specified in the General tab of the
ALT2GXB MegaWizard. Similarly, connect pll_inclk_alt and
rx_cruclk_alt
to the clock source that provides the clock for the
protocol mode specified in the Reconfig tab of the ALT2GXB
MegaWizard.
1
If you do not specify pins for tx_dataout and rx_datain for
the transceiver channel, the Quartus II software selects a channel
and generates a MIF for that channel. However, the MIF can still
be used for any transceiver channel.