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參數(shù)資料
| 型號： | EP2SGX30DF780C5 |
| 廠商： | Altera |
| 文件頁數(shù)： | 312/1486頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II GX 30K 780-FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 9 |
| 系列： | Stratix® II GX |
| LAB/CLB數(shù)： | 1694 |
| 邏輯元件/單元數(shù)： | 33880 |
| RAM 位總計： | 1369728 |
| 輸入/輸出數(shù)： | 361 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 780-BBGA |
| 供應商設備封裝： | 780-FBGA（29x29） |
| 其它名稱： | 544-1753 |
Altera Corporation
12–13
October 2007
Stratix II GX Device Handbook, Volume 2
DSP Blocks in Stratix II & Stratix II GX Devices
Saturation and Rounding
The DSP blocks have hardware support to perform optional saturation
and rounding after each 18 × 18 multiplier for Q1.15 input formats.
1
Designs must use 18 × 18 multipliers for the saturation and
rounding options because the Q1.15 input format requires 16-bit
input widths.
1
Q1.15 input format multiplication requires signed multipliers.
The most significant bit (MSB) in the Q1.15 input format
represents the value’s sign bit. Use signed multipliers to ensure
the proper sign extension during multiplication.
The Q1.15 format uses 16 bits to represent each fixed point input. The
MSB is the sign bit, and the remaining 15-bits are used to represent the
value after the decimal place (or the fractional value). This Q1.15 value is
equivalent to an integer number representation of the 16-bits divided by
215, as shown in the following equations.
All Q1.15 numbers are between –1 and 1.
When performing multiplication, even though the Q1.15 input only uses
16 of the 18 multiplier inputs, the entire 18-bit input bus is transmitted to
the multiplier. This is like a 1.17 input, where the two least significant bits
(LSBs) are always 0.
The multiplier output will be a 2.34 value (36 bits total) before performing
any rounding or saturation. The two MSBs are sign bits. Since the output
only requires one sign bit, you can ignore one of the two MSBs, resulting
in a Q1.34 value before rounding or saturation.
When the design performs saturation, the multiplier output gets
saturated to 0x7FFFFFFF in a 1.31 format. This uses bits [34..3] of the
overall 36-bit multiplier output. The three LSBs are set to 0.
The DSP block obtains the mult_is_saturated or
accum_is_saturated
overflow signal value from the LSB of the
multiplier or accumulator output. Therefore, whenever saturation occurs,
the LSB of the multiplier or accumulator output will send a 1 to the
1
2
= 1 100 0000 0000 0000 =
0x4000
215
1
8
= 0 001 0000 0000 0000 =
0x1000
215
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP2SGX30DF780C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 1694 LABs 361 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX30DF780I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 1694 LABs 361 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX30DF780I4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 1694 LABs 361 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX60 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Package Information Datasheet for Mature Altera Devices |
| EP2SGX60C | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix II GX Device |
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