1–42
Altera Corporation
Stratix II Device Handbook, Volume 2
July 2009
Advanced Features
All the switchover ports shown in
Table 1–15 are supported in the
altpll
megafunction in the Quartus II software. The altpll
megafunction supports two methods for clock switchover:
■
When selecting an enhanced PLL, you can enable both the automatic
and the manual switchover, making all the clock switchover ports
available.
■
When selecting a fast PLL, you can use only enable the manual clock
switchover option to select between inclk0 or inclk1. The
clkloss
, activeclock and the clkbad0, and clkbad1 signals
are not available when manual switchover is selected.
If the primary and secondary clock frequencies are different, the
Quartus II software selects the proper parameters to keep the VCO within
the recommended frequency range.
f
For more information about PLL software support in the Quartus II
Guidelines
Use the following guidelines to design with clock switchover in PLLs.
■
When using automatic switchover, the clkswitch signal has a
minimum pulse width based on the two reference clock periods. The
CLKSWITCH
pulse width must be greater than or equal to the period
of the current reference clock (tfrom_clk) multiplied by two plus the
rounded-up version of the ratio of the two reference clock periods.
For example, if tto_clk is equal to tfrom_clk, then the CLKSWITCH pulse
width should be at least three times the period of the clock pulse.
t
CLKSWITCHCH
min tfrom_clk [2 + intround_up (tto_clk
tfrom_clk)]
Signal to indicate which clock (0 =
inclk0
, 1= inclk1) is driving the PLL.
PLL
Logic array
(1)
These ports are only available for enhanced PLLs and in auto mode and when using automatic switchover.
Table 1–15. altpll Megafunction Clock Switchover Signals
(Part 2 of 2)
Port
Description
Source
Destination
