Ensure that D > 2S to min" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EP2S90F1020C5N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 729/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 90K 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 6
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 4548
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 90960
RAM 浣嶇附瑷�(j矛)锛� 4520488
杓稿叆/杓稿嚭鏁�(sh霉)锛� 758
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1020-FBGA锛�33x33锛�
鍏跺畠鍚嶇ū锛� 544-1918
EP2S90F1020C5N-ND
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�绗�767闋�绗�768闋�
Altera Corporation
11鈥�19
May 2007
Stratix II Device Handbook, Volume 2
High-Speed Board Layout Guidelines
鈻�
Ensure that D > 2S to minimize the crosstalk between the two
differential pairs.
鈻�
Place the differential traces S = 3H as they leave the device to
minimize reflection noise.
鈻�
Keep the length of the two differential traces the same to minimize
the skew and phase difference.
鈻�
Avoid using multiple vias because they can cause impedance
mismatch and inductance.
Termination
Schemes
Mismatched impedance causes signals to reflect back and forth along the
lines, which causes ringing at the load receiver. The ringing reduces the
dynamic range of the receiver and can cause false triggering. To eliminate
reflections, the impedance of the source (ZS) must equal the impedance of
the trace (Zo), as well as the impedance of the load (ZL). This section
discusses the following signal termination schemes:
鈻�
Simple parallel termination
鈻�
Thevenin parallel termination
鈻�
Active parallel termination
鈻�
Series-RC parallel termination
鈻�
Series termination
鈻�
Differential pair termination
Simple Parallel Termination
In a simple parallel termination scheme, the termination resistor (RT) is
equal to the line impedance. Place the RT as close to the load as possible
to be efficient (see Figure 11鈥�22).
Figure 11鈥�22. Simple Parallel Termination
The stub length from the RT to the receiver pin and pads should be as
small as possible. A long stub length causes reflections from the receiver
pads, resulting in signal degradation. If your design requires a long
termination line between the terminator and receiver, the placement of
the resistor becomes important. For long termination line lengths, use
fly-by termination (see Figure 11鈥�23).
Zo = 50 惟
RT = Zo
SL
Stub
S = Source
L = Load
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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EP2S90F1020I4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90F1020I4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90F1508C3 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 902 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90F1508C3ES 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:Stratix II Device Family Data Sheet
EP2S90F1508C3N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 902 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256