7–2
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
Introduction
The configuration scheme is selected by driving the Stratix II or
Stratix II GX device MSEL pins either high or low as shown in
Table 7–1.The MSEL pins are powered by the VCCIO power supply of the bank they
reside in. The MSEL[3..0] pins have 9-k internal pull-down resistors
that are always active. During power-on reset (POR) and during
reconfiguration, the MSEL pins have to be at LVTTL VIL and VIH levels to
be considered a logic low and logic high.
1
To avoid any problems with detecting an incorrect configuration
scheme, hard-wire the MSEL[] pins to VCCPD and GND, without
any pull-up or pull-down resistors. Do not drive the MSEL[]
pins by a microprocessor or another device.
Table 7–1. Stratix II and Stratix II GX Configuration Schemes (Part 1 of 2)
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
Fast passive parallel (FPP)
0000
Passive parallel asynchronous (PPA)
0001
Passive serial (PS)
0010
Remote system upgrade FPP
(1)0100
Remote system upgrade PPA
(1)0101
Remote system upgrade PS
(1)0110
1000
Remote system upgrade fast AS (40 MHz)
(2)1001
FPP with decompression and/or design security
1011
Remote system upgrade FPP with decompression
and/or design security feature enabled
(1),
(3)1100
1101
Remote system upgrade AS (20 MHz)
(2)1110
JTAG-based configuration
(5)
