Altera Corporation
6–25
January 2008
Stratix II Device Handbook, Volume 2
DSP Blocks in Stratix II and Stratix II GX Devices
The 36-bit multiplier is useful for applications requiring more than 18-bit
precision, for example, for mantissa multiplication of precision floating-
point arithmetic applications.
Multiply Accumulate Mode
In multiply accumulate mode, the output of the multiplier stage feeds the
adder/output block which is configured as an accumulator or subtractor.
Figure 6–10 shows the DSP block configured to operate in multiply
accumulate mode.
Figure 6–10. Multiply Accumulate Mode
(1)
The signa and signb signals are the same in the multiplier stage and the adder/output block.
(2)
These signals are not registered or registered once to match the data path pipeline.
(3)
You can send these signals through either one or two pipeline registers.
(4)
These signals match the latency of the data path.
A single DSP block can implement up to two independent 18-bit
multiplier accumulators. The Quartus II software implements smaller
multiplier accumulators by tying the unused lower-order bits of the 18-bit
multiplier to ground.
The multiplier accumulator output can be up to 52-bits wide to account
for a 36-bit multiplier result with 16-bits of accumulation. In this mode,
the DSP block uses output registers and the accum_sload and overflow
CLRN
DQ
ENA
CLRN
DQ
ENA
Data A
Data B
Data Out
overflow
shiftoutb
shiftouta
shiftina
shiftinb
CLRN
DQ
ENA
CLRN
DQ
ENA
Accumulator
accum_sload (3)
DQ
ENA
Q1.15
Round/
Saturate
accum_sload_upper_data (3)
Q1.15
Round/
Saturate
mult_saturate (2)
mult_round (2)
accum_saturate (3)
accum_round (3)
addnsub (3)
signa (1), (3)
signb (1), (3)
signa (1), (2)
signb (1), (2)
aclr[3..0]
clock[3..0]
ena[3..0]
mult_is_saturated (4)
accum_is_saturated (4)
DQ
ENA
DQ
ENA
DQ
ENA
