
1–58
Altera Corporation
Stratix II Device Handbook, Volume 2
July 2009
Board Layout
Figure 1–36. PLL Power Schematic for Stratix II and Stratix II GX PLLs
(1)
Applies to PLLs 1 through 12.
VCCD
The digital power and ground pins are labeled VCCD_PLL<PLL number>
and GND. The VCCD pin supplies the power for the digital circuitry in the
PLL. Connect these VCCD pins to the quietest digital supply on the board.
In most systems, this is the digital 1.2-V supply supplied to the device’s
VCCINT pins. Connect the VCCD pins to a power supply even if you do not
use the PLL. When connecting the VCCD pins to VCCINT, you do not need
any filtering or isolation. You can connect the GND pins directly to the
same ground plane as the device’s digital ground. See
Figure 1–36.External Clock Output Power
Enhanced PLLs 5, 6, 11, and 12 also have isolated power pins for their
dedicated external clock outputs (VCC_PLL5_OUT, VCC_PLL6_OUT,
VCC_PLL11_OUT
and VCC_PLL12_OUT, respectively). Since the
VCCA_PLL #
GNDA_PLL #
VCCD_PLL #
GND
1.2-V
Supply
Repeat for Each
PLL Power &
Ground Set
Stratix II Device
Ferrite
Bead
0.1
μF
0.001
μF
GND
10
μF
GND
(1)
VCCINT