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參數(shù)資料
| 型號(hào)： | EP2S30F672C4N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 506/768頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II FPGA 30K 672-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | Stratix® II |
| LAB/CLB數(shù)： | 1694 |
| 邏輯元件/單元數(shù)： | 33880 |
| RAM 位總計(jì)： | 1369728 |
| 輸入/輸出數(shù)： | 500 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 672-BBGA |
| 供應(yīng)商設(shè)備封裝： | 672-BGA（27x27） |
| 其它名稱(chēng)： | 544-1897 EP2S30F672C4N-ND |
7–2
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
Introduction
The configuration scheme is selected by driving the Stratix II or
Stratix II GX device MSEL pins either high or low as shown in Table 7–1.
The MSEL pins are powered by the VCCIO power supply of the bank they
reside in. The MSEL[3..0] pins have 9-k internal pull-down resistors
that are always active. During power-on reset (POR) and during
reconfiguration, the MSEL pins have to be at LVTTL VIL and VIH levels to
be considered a logic low and logic high.
1
To avoid any problems with detecting an incorrect configuration
scheme, hard-wire the MSEL[] pins to VCCPD and GND, without
any pull-up or pull-down resistors. Do not drive the MSEL[]
pins by a microprocessor or another device.
Table 7–1. Stratix II and Stratix II GX Configuration Schemes (Part 1 of 2)
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
Fast passive parallel (FPP)
0000
Passive parallel asynchronous (PPA)
0001
Passive serial (PS)
0010
Remote system upgrade FPP (1)
0100
Remote system upgrade PPA (1)
0101
Remote system upgrade PS (1)
0110
Fast AS (40 MHz) (2)
1000
Remote system upgrade fast AS (40 MHz) (2)
1001
FPP with decompression and/or design security
feature enabled (3)
1011
Remote system upgrade FPP with decompression
1100
AS (20 MHz) (2)
1101
Remote system upgrade AS (20 MHz) (2)
1110
JTAG-based configuration (5)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2S30F672C5 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix II 1694 LABs 500 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S30F672C5AA | 制造商:Altera Corporation 功能描述:FPGA Stratix |
| EP2S30F672C5N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix II 1694 LABs 500 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S30F672C5RB | 制造商:Altera Corporation 功能描述:FPGA Stratix |
| EP2S30F672I4 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix II 1694 LABs 500 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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