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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S30F672C4
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 195/768闋�
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鎻忚堪锛� IC STRATIX II FPGA 30K 672-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 10
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LAB/CLB鏁�(sh霉)锛� 1694
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 33880
RAM 浣嶇附瑷堬細 1369728
杓稿叆/杓稿嚭鏁�(sh霉)锛� 500
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 672-BGA锛�27x27锛�
鍏跺畠鍚嶇ū锛� 544-1125
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�绗�767闋�绗�768闋�
1鈥�10
Altera Corporation
Stratix II Device Handbook, Volume 2
July 2009
Enhanced PLLs
Figure 1鈥�6. Enhanced PLL Ports
(1)
Enhanced and fast PLLs share this input pin.
(2)
These are either single-ended or differential pins.
(3)
The primary and secondary clock input can be fed from any one of four clock pins located on the same side of the
device as the PLL.
(4)
Can drive to the global or regional clock networks or the dedicated external clock output pins.
(5)
These dedicated output clocks are fed by the C[5..0] counters.
Tables 1鈥�4 and 1鈥�5 describe all the enhanced PLL ports.
clkswitch
scandata
scanclk
pllena
C[5..0]
locked
Physical Pin
clkloss
areset
pfdena
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
scandone
pll_out0p
scandataout
fbin
clkbad[1..0]
(1)
(2), (3)
pll_out0n
pll_out1p
pll_out1n
pll_out2p
pll_out2n
(5)
scanwrite
scanread
(5)
activeclock
inclk0
inclk1
(4)
(2), (3)
Table 1鈥�4. Enhanced PLL Input Signals (Part 1 of 2)
Port
Description
Source
Destination
inclk0
Primary clock input to the PLL.
Pin or another PLL
n counter
inclk1
Secondary clock input to the PLL.
Pin or another PLL
n counter
fbin
External feedback input to the PLL.
Pin
PFD
pllena
Enable pin for enabling or disabling
all or a set of PLLs. Active high.
Pin
General PLL control
signal
clkswitch
Switch-over signal used to initiate
external clock switch-over control.
Active high.
Logic array
PLL switch-over circuit
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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EP2S30F672C5AA 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix
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EP2S30F672C5RB 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix