
5–64
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
Timing Model
1.5-V
Differential
HSTL Class II
16 mA
tOP
881
924
1431
1501
1644
1734
ps
tDIP
901
946
1497
1571
1720
1824
ps
18 mA
tOP
884
927
1439
1510
1654
1744
tDIP
904
949
1505
1580
1730
1834
20 mA
tOP
886
929
1450
1521
1666
1757
tDIP
906
951
1516
1591
1742
1847
(1)
This is the default setting in the Quartus II software.
(2)
These I/O standards are only supported on DQS pins.
(3)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(4)
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 1 of 3)
I/O Standard
Drive
Strength
Parameter
Minimum Timing
-3
Speed
Grade
-3
Speed
Grade
-4
Speed
Grade
-5
Speed
Grade
Unit
Industrial
Commercial
LVTTL
4 mA
tOP
1267
1328
2655
2786
3052
3189
ps
tDI P
1225
1285
2600
2729
2989
3116
ps
8 mA
tOP
1144
1200
2113
2217
2429
2549
ps
tDIP
1102
1157
2058
2160
2366
2476
ps
12 mA
tOP
1091
1144
2081
2184
2392
2512
ps
tDIP
1049
1101
2026
2127
2329
2439
ps
LVCMOS
4 mA
tOP
1144
1200
2113
2217
2429
2549
ps
tDI P
1102
1157
2058
2160
2366
2476
ps
tOP
1044
1094
1853
1944
2130
2243
ps
tDIP
1002
1051
1798
1887
2067
2170
ps
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 8 of 8)
I/O Standard
Drive
Strength
Parameter
Minimum Timing
-3
Speed
Grade
(3)
-3
Speed
Grade
(4)
-4
Speed
Grade
-5
Speed
Grade
Unit
Industrial
Commercial