鍨嬭櫉锛� | EP2S30F672C3 |
寤犲晢锛� | Altera |
鏂囦欢闋佹暩锛� | 38/768闋� |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC STRATIX II FPGA 30K 672-FBGA |
鐢㈠搧鍩硅〒妯″锛� | Three Reasons to Use FPGA's in Industrial Designs |
妯欐簴鍖呰锛� | 10 |
绯诲垪锛� | Stratix® II |
LAB/CLB鏁革細 | 1694 |
閭忚集鍏冧欢/鍠厓鏁革細 | 33880 |
RAM 浣嶇附瑷堬細 | 1369728 |
杓稿叆/杓稿嚭鏁革細 | 500 |
闆绘簮闆诲锛� | 1.15 V ~ 1.25 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 85°C |
灏佽/澶栨锛� | 672-BBGA |
渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 672-BGA锛�27x27锛� |
鍏跺畠鍚嶇ū锛� | 544-1895 EP2S30F672C3-ND |
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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EP2AGX95DF25C5N | IC ARRIA II GX FPGA 95K 572FBGA |
EP1S20F484C5 | IC STRATIX FPGA 20K LE 484-FBGA |
445705-4 | CONN D-SUB RCPT HSING 3C3 MIX |
ACC50DRXS-S734 | CONN EDGECARD 100PS DIP .100 SLD |
204501-5 | CONN D-SUB PLUG HD 15P SER 90 |
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁� |
鍙冩暩鎻忚堪 |
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EP2S30F672C3N | 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S30F672C4 | 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S30F672C4N | 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S30F672C5 | 鍔熻兘鎻忚堪:FPGA - 鐝惧牬鍙法绋嬮杸闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁搁噺: 閭忚集濉婃暩閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S30F672C5AA | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix |