參數(shù)資料
| 型號： | EP2S180F1508C3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 438/768頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX II FPGA 180K 1508FBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 7 |
| 系列： | Stratix® II |
| LAB/CLB數(shù)： | 8970 |
| 邏輯元件/單元數(shù)： | 179400 |
| RAM 位總計： | 9383040 |
| 輸入/輸出數(shù)： | 1170 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1508-BBGA |
| 供應商設備封裝： | 1508-FBGA（30x30） |
| 配用： | 544-1701-ND - DSP PRO KIT W/SII EP2S180N |
| 其它名稱： | 544-1886 EP2S180F1508C3N-ND Q2675539 |
Altera Corporation
5–9
January 2008
Stratix II Device Handbook, Volume 2
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
The deserializer, like the serializer, can also be bypassed to support DDR
(2) and SDR (1) operations. The DPA and data realignment circuit
cannot be used when the deserializer is bypassed. The IOE contains two
data input registers that can operate in DDR or SDR mode. The clock
source for the registers in the IOE can come from any routing resource,
from the fast PLL, or from the enhanced PLL. Figure 5–7 shows the
bypass path.
Figure 5–7. Deserializer Bypass
Receiver Data Realignment Circuit
The data realignment circuit aligns the word boundary of the incoming
data by inserting bit latencies into the serial stream. An optional
RX_CHANNEL_DATA_ALIGN
port controls the bit insertion of each
receiver independently controlled from the internal logic. The data slips
one bit for every pulse on the RX_CHANNEL_DATA_ALIGN port. The
following are requirements for the RX_CHANNEL_DATA_ALIGN port:
■
The minimum pulse width is one period of the parallel clock in the
logic array.
■
The minimum low time between pulses is one period of parallel
clock.
■
There is no maximum high or low time.
■
Valid data is available two parallel clock cycles after the rising edge
of RX_CHANNEL_DATA_ALIGN.
rx_in
IOE
Deserializer
DPA
Circuitry
PLD Logic
Array
IOE Supports SDR, DDR, or
Non-Registered Data Path
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP2S180F1508C4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 8970 LABs 1170 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S180F1508C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 8970 LABs 1170 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S180F1508C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 8970 LABs 1170 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S180F1508C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 8970 LABs 1170 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S180F1508I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 8970 LABs 1170 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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