
7–106
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
Conclusion
Stratix II and Stratix II GX devices can be configured in a number of
different schemes to fit your system’s need. In addition, configuration
bitstream encryption, configuration data decompression, and remote
system upgrade support supplement the Stratix II and Stratix II GX
configuration solution.
Referenced
Documents
This chapter references the following documents:
■
ByteBlasterMV Download Cable User Guide
■
in volume 2 of the Configuration Handbook.
■
Configuration Handbook
■
Device Handbook
■
Device Handbook
■
volume 2 of the Configuration Handbook
■
Devices chapter in volume 2 of the Stratix II Device Handbook ■
Devices chapter in volume 2 of the Stratix II GX Device Handbook ■
TCK
N/A
Input
The clock input to the BST circuitry. Some operations occur at the rising
edge, while others occur at the falling edge. The TCK pin is powered by the
3.3-V VCCPD supply.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting TCK to GND.
TRST
N/A
Input
Active-low input to asynchronously reset the boundary-scan circuit. The
TRST
pin is optional according to IEEE Std. 1149.1. The TRST pin is
powered by the 3.3-V VCCPD supply.
If the JTAG interface is not required on the board, the JTAG circuitry can be
disabled by connecting the TRST pin to GND.
Table 7–24. Dedicated JTAG Pins (Part 2 of 2)
Pin Name User Mode Pin Type
Description