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參數(shù)資料
| 型號： | EP2S130F1020C4N |
| 廠商： | Altera |
| 文件頁數(shù)： | 17/768頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX II FPGA 130K 1020FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 6 |
| 系列： | Stratix® II |
| LAB/CLB數(shù)： | 6627 |
| 邏輯元件/單元數(shù)： | 132540 |
| RAM 位總計： | 6747840 |
| 輸入/輸出數(shù)： | 742 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1020-BBGA |
| 供應商設備封裝： | 1020-FBGA（33x33） |
| 其它名稱： | 544-1866 EP2S130F1020C4N-ND |
Altera Corporation
2–95
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
For JTAG chains, the TDO pin of the first device drives the TDI pin of the
second device in the chain. The VCCSEL input on JTAG input I/O cells
(TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the
3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the
VCCIO of the TDO bank from the first device to match the VCCSEL settings
for TDI on the second device, but that may not be possible depending on
the application. Table 2–20 contains board design recommendations to
ensure proper JTAG chain operation.
Table 2–19. Board Design Recommendations for nCEO
nCE Input Buffer Power in I/O
Bank 3
Stratix II nCEO VCCIO Voltage Level in I/O Bank 7
VCCIO =
3.3 V
VCCIO =
2.5 V
VCCIO =
1.8 V
VCCIO =
1.5 V
VCCIO =
1.2 V
VCCSEL
high
(VCCIO Bank 3 = 1.5 V)
v (5)
vv
VCCSEL
high
(VCCIO Bank 3 = 1.8 V)
vv
Level shifter
required
VCCSEL
low
(nCE Powered by VCCPD = 3.3V)
v
v (4)
v (6)
Level shifter
required
Level shifter
required
Notes to Table 2–19:
(1)
Input buffer is 3.3-V tolerant.
(2)
The nCEO output buffer meets VOH (MIN) = 2.4 V.
(3)
Input buffer is 2.5-V tolerant.
(4)
The nCEO output buffer meets VOH (MIN) = 2.0 V.
(5)
Input buffer is 1.8-V tolerant.
(6)
An external 250-
Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 1 of 2)
Device
TDI Input
Buffer Power
Stratix II TDO VCCIO Voltage Level in I/O Bank 4
VCCIO = 3.3 V VCCIO = 2.5 V VCCIO = 1.8 V VCCIO = 1.5 V VCCIO = 1.2 V
Stratix II
Always
VCCPD (3.3V)
v (1)
v (2)
v (3)
Level shifter
required
Level shifter
required
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP2S130F1020C4RB | 制造商:Altera Corporation 功能描述:FPGA Stratix |
| EP2S130F1020C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1020C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1020I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1020I4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II 6627 LABs 742 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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