參數(shù)資料
型號: EP20K600EFC1020-1
元件分類: CPU監(jiān)測
英文描述: RTC Module With CPU Supervisor
中文描述: 時(shí)鐘模塊CPU監(jiān)控
文件頁數(shù): 52/114頁
文件大?。?/td> 1623K
代理商: EP20K600EFC1020-1
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K600EFC1020-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K600EFC1020-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K600EFC1020-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K600EFC1020-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K600EFC1020-2X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA