參數(shù)資料
型號(hào): EP20K400EFI672-3ES
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 76/114頁
文件大?。?/td> 1623K
代理商: EP20K400EFI672-3ES
64
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
VOL
3.3-V low-level TTL output voltage IOL = 12 mA DC,
VCCIO =3.00 V (10)
0.45
V
3.3-V low-level CMOS output
voltage
IOL = 0.1 mA DC,
VCCIO =3.00 V (10)
0.2
V
3.3-V low-level PCI output voltage IOL = 1.5 mA DC,
VCCIO = 3.00 to 3.60 V
0.1
× V
CCIO
V
2.5-V low-level output voltage
IOL = 0.1 mA DC,
VCCIO =2.30 V (10)
0.2
V
IOL = 1 mA DC,
VCCIO =2.30 V (10)
0.4
V
IOL = 2 mA DC,
VCCIO =2.30 V (10)
0.7
V
II
Input pin leakage current
VI = 5.75 to –0.5 V
–10
10
A
IOZ
Tri-stated I/O pin leakage current
V O = 5.75 to –0.5 V
–10
10
A
ICC0
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade (11)
10
mA
VI = ground, no load, no
toggling inputs,
-2, -3 speed grades (11)
5mA
RCONF
Value of I/O pin pull-up resistor
before and during configuration
VCCIO = 3.0 V (12)
20
50
k
VCCIO = 2.375 V (12)
30
80
k
Table 30. APEX 20K 5.0-V Tolerant Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on dedicated
clock pin
VIN = 0 V, f = 1.0 MHz
12
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
8
pF
Table 29. APEX 20K 5.0-V Tolerant Device DC Operating Conditions (Part 2 of 2)
Notes (6), (7)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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