Notes to Figure 8: (1) LEs in " />
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    參數(shù)資料
    型號(hào): EP20K400EFC672-2N
    廠商: Altera
    文件頁數(shù): 28/117頁
    文件大?。?/td> 0K
    描述: IC APEX 20KE FPGA 400K 672-FBGA
    產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
    標(biāo)準(zhǔn)包裝: 40
    系列: APEX-20K®
    LAB/CLB數(shù): 1664
    邏輯元件/單元數(shù): 16640
    RAM 位總計(jì): 212992
    輸入/輸出數(shù): 488
    門數(shù): 1052000
    電源電壓: 1.71 V ~ 1.89 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 672-BBGA
    供應(yīng)商設(shè)備封裝: 672-BGA(27x27)
    18
    Altera Corporation
    APEX 20K Programmable Logic Device Family Data Sheet
    Figure 8. APEX 20K LE Operating Modes
    Notes to Figure 8:
    (1)
    LEs in normal mode support register packing.
    (2)
    There are two LAB-wide clock enables per LAB.
    (3)
    When using the carry-in in normal mode, the packed register feature is unavailable.
    (4)
    A register feedback multiplexer is available on LE1 of each LAB.
    (5)
    The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
    LEs other than the second LE in an LAB.
    (6)
    The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
    PRN
    CLRN
    DQ
    4-Input
    LUT
    Carry-In
    (3)
    Cascade-Out
    Cascade-In
    LE-Out
    Normal Mode (1)
    PRN
    CLRN
    DQ
    Cascade-Out
    Cascade-In
    3-Input
    LUT
    Carry-In
    3-Input
    LUT
    Carry-Out
    Arithmetic Mode
    Counter Mode
    data1
    (5)
    data2
    (5)
    PRN
    CLRN
    DQ
    Carry-In
    LUT
    3-Input
    LUT
    Carry-Out
    data3 (data)
    Cascade-Out
    Cascade-In
    LAB-Wide
    Synchronous
    Load
    (6)
    LAB-Wide
    Synchronous
    Clear
    (6)
    (4)
    LE-Out
    ENA
    LAB-Wide
    Clock Enable
    (2)
    ENA
    LAB-Wide
    Clock Enable
    (2)
    ENA
    LAB-Wide
    Clock Enable
    (2)
    data1
    data2
    data1
    data2
    data3
    data4
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