Tables 91 through 96 describe f
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EP20K400EBC652-3N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 6/117闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC APEX 20KE FPGA 400K 652-BGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 12
绯诲垪锛� APEX-20K®
LAB/CLB鏁�(sh霉)锛� 1664
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 16640
RAM 浣嶇附瑷�(j矛)锛� 212992
杓稿叆/杓稿嚭鏁�(sh霉)锛� 488
闁€鏁�(sh霉)锛� 1052000
闆绘簮闆诲锛� 1.71 V ~ 1.89 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 652-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 652-BGA锛�45x45锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�鐣�(d膩ng)鍓嶇6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�
Altera Corporation
103
APEX 20K Programmable Logic Device Family Data Sheet
Tables 91 through 96 describe fMAX LE Timing Microparameters, fMAX
ESB Timing Microparameters, fMAX Routing Delays, Minimum Pulse
Width Timing Parameters, External Timing Parameters, and External
Bidirectional Timing Parameters for EP20K600E APEX 20KE devices.
Table 90. EP20K400E External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU BIDIR
2.93
3.23
3.44
ns
tI N H B ID IR
0.00
ns
tOUT C OBIDIR
2.00
5.25
2.00
5.79
2.00
6.32
ns
tXZ BIDIR
5.95
6.77
7.12
ns
tZX BIDIR
5.95
6.77
7.12
ns
tINSU BIDIRPL L
4.31
4.76
-
ns
tI N H B ID IR P L L
0.00
-
ns
tOUT C OBIDIRP LL
0.50
2.25
0.50
2.45
-
ns
tXZ BIDIRPL L
2.94
3.43
-
ns
tZX BIDIRPL L
2.94
3.43
-
ns
Table 91. EP20K600E fMAX LE Timing Microparameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tSU
0.16
0.17
ns
tH
0.29
0.33
0.37
ns
tCO
0.65
0.38
0.49
ns
tLUT
0.70
1.00
1.30
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
207252-2 CONN D-SUB PLUG 9POS CRIMP
EP20K400EBC652-3 IC APEX 20KE FPGA 400K 652-BGA
EP2AGX65CU17C6 IC ARRIA II GX FPGA 65K 358UBGA
M1AFS1500-FG676I IC FPGA 8MB FLASH 1.5M 676-FBGA
M1AFS1500-FGG676I IC FPGA 8MB FLASH 1.5M 676-FBGA
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
EP20K400EBI652-1ES 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:FPGA
EP20K400EBI652-2ES 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:FPGA
EP20K400EBI652-2X 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 CPLD - APEX 20K 1664 Macros 488 IO RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP20K400EBI652-3ES 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:FPGA
EP20K400EFC672-1 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 CPLD - APEX 20K 1664 Macros 488 IO RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256