參數(shù)資料
型號(hào)： EP20K400CB652I7ES
元件分類： 電源監(jiān)測(cè)
英文描述： Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述： 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù)： 29/114頁
文件大?。?/td> 1623K
代理商： EP20K400CB652I7ES
Altera Corporation
21
APEX 20K Programmable Logic Device Family Data Sheet
Figure 9. APEX 20K Interconnect Structure
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10 shows how the FastTrack Interconnect uses the local
interconnect to drive LEs within MegaLAB structures.
MegaLAB
I/O
MegaLAB
I/O
MegaLAB
I/O
Column
Interconnect
Column
Interconnect
Row
Interconnect
相關(guān)PDF資料
PDF描述
EP20K400CB652I8ES Dual Voltage Monitor with Intergrated CPU Supervisor
EP20K400CB652I9ES Dual Voltage Monitor with Intergrated CPU Supervisor
EP20K400CF672I7ES Dual Voltage Monitor with Intergrated CPU Supervisor
EP20K400CF672I8ES Dual Voltage Monitor with Intergrated CPU Supervisor
EP20K400CF672I9ES Dual Voltage Monitor with Intergrated CPU Supervisor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K400CB652I8 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400CB652I8ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K400CB652I9ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K400CF672C7 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400CF672C7GA 制造商:Altera Corporation 功能描述:
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