Notes to Table 15: (1) The PLL input frequency range for the EP20K10" />
參數(shù)資料
型號： EP20K200EFI484-2X
廠商： Altera
文件頁數(shù)： 65/117頁
文件大?。?/td> 0K
描述： IC APEX 20KE FPGA 200K 484-FBGA
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 60
系列： APEX-20K®
LAB/CLB數(shù)： 832
邏輯元件/單元數(shù)： 8320
RAM 位總計： 106496
輸入/輸出數(shù)： 376
門數(shù)： 404000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BGA
供應商設備封裝： 484-FBGA（23x23）
其它名稱： 544-2093
Altera Corporation
51
APEX 20K Programmable Logic Device Family Data Sheet
Notes to Table 15:
(1)
The PLL input frequency range for the EP20K100-1X device for 1x multiplication is 25 MHz to 175 MHz.
(2)
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is
supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock
time is less than the configuration time.
(4)
The jitter specification is measured under long-term observation.
(5)
If the input clock stability is 100 ps, tJITTER is 250 ps.
Table 16 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
tSKEW
Skew delay between related
ClockLock/ClockBoost-generated clocks
500
ps
tJITTER
Jitter on ClockLock/ClockBoost-generated clock
200
ps
tINCLKSTB
Input clock stability (measured between adjacent
clocks)
50
ps
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade Devices
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
170
MHz
fCLK1
Input clock frequency (ClockBoost clock multiplication
factor equals 1)
25
170
MHz
fCLK2
Input clock frequency (ClockBoost clock multiplication
factor equals 2)
16
80
MHz
fCLK4
Input clock frequency (ClockBoost clock multiplication
factor equals 4)
10
34
MHz
tOUTDUTY
Duty cycle for ClockLock/ClockBoost-generated clock
40
60
%
fCLKDEV
Input deviation from user specification in the Quartus II
software (ClockBoost clock multiplication factor equals
one) (1)
25,000 (2)
PPM
tR
Input rise time
5ns
tF
Input fall time
5ns
tLOCK
Time required for ClockLock/ ClockBoost to acquire
lock (3)
10
s
tSKEW
Skew delay between related ClockLock/ ClockBoost-
generated clock
500
ps
tJITTER
Jitter on ClockLock/ ClockBoost-generated clock (4)
200
ps
tINCLKSTB
Input clock stability (measured between adjacent
clocks)
50
ps
相關PDF資料
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