
ESS Technology, Inc.
SAM0378-053001
7
ES4228/ES4227 PRODUCT BRIEF
RSD
33
O
I
Dual-purpose pin. RSD is the receive audio data input.
SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output.
See the table for pin number 23.
Dual-purpose pin. RBCK is the receive audio bit clock.
SER_IN is the serial input DSC mode.
0 - Parallel DSC mode.
1 - Serial DSC mode.
Audio Analog Ground.
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V.
Bypass to analog ground with 47
μ
F electrolytic in parallel with 0.1
μ
F.
DAC and ADC maximum reference. Bypass to VCMR with 10
μ
F in parallel with 0.1
μ
F.
Analog VCC, 5 V.
SEL_PLL0
RBCK
37
O
I
SER_IN
VSSAA
41,51
42
I
I
VCM
VREFP
VCCAA
AOR+,
AOR-
AOL-, AOL+
MIC2
MIC1
43
44
I
I
45, 46
O
Right channel output.
47, 48
49
50
52
O
I
I
I
Left channel output.
Microphone input 2.
Microphone input 1.
Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to
analog ground with 0.1
μ
F.
DAC and ADC minimum reference. Bypass to VCMR with 10
μ
F in parallel with 0.1
μ
F.
Full scale DAC current adjustment.
Compensation pin.
Video analog ground
Modulated chrominance output.
5.0V video power supply.
Y luminance data bus for screen video port.
Composite video output.
Audio CAP
27 MHz crystal output.
27 MHz crystal input.
13.5 MHz pixel clock.
Doubled 27 MHz pixel clock.
Horizontal sync.
Vertical sync.
VREF
VREFM
RSET
COMP
VSSAV
CDAC
VCCAV
YDAC
VDAC
ACAP
XOUT
XIN
PCLK
2XPCLK
HSYNC#
VSYNC#
53
54
55
I
I
I
I
56:57, 62:63
58
59, 60
61
64
65
71
74
79
80
82
84
86:89, 92, 94, 96,
98
O
I
O
O
I
O
I
I/O
I/O
O
O
I
YUV[7:0]
YUV data bus for screen video port.
Table 2 ES4227 Pin Descriptions List (Continued)
Name
Number
I/O
Definition