參數(shù)資料
型號: EP20K200CP240I9
英文描述: 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 28-CSP
中文描述: 專用集成電路
文件頁數(shù): 64/114頁
文件大小: 1623K
代理商: EP20K200CP240I9
Altera Corporation
53
APEX 20K Programmable Logic Device Family Data Sheet
Tables 17 and 18 summarize the ClockLock and ClockBoost parameters
for APEX 20KE devices.
Table 17. APEX 20KE ClockLock & ClockBoost Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5ns
tF
Input fall time
5ns
tINDUTY
Input duty cycle
40
60
%
tINJITTER
Input jitter peak-to-peak
2
% of input
period
peak-to-
peak
tOUTJITTER Jitter on ClockLock or ClockBoost-
generated clock
0.35
% of
output period
RMS
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
45
55
%
tLOCK (2),
Time required for ClockLock or
ClockBoost to acquire lock
40
s
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