參數(shù)資料
型號: EP20K200CF672C8
英文描述: 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 28-CerDIP
中文描述: 專用集成電路
文件頁數(shù): 52/114頁
文件大?。?/td> 1623K
代理商: EP20K200CF672C8
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
相關PDF資料
PDF描述
EP20K200CF672C9 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 28-CerDIP
EP20K200CF672I7 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 28-CerDIP
EP20K200CF672I8 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -40°C to 85°C; Package: 32-CLCC
EP20K200CF672I9 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 32-LCC
EP20K200CP208C7 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 32-LCC
相關代理商/技術參數(shù)
參數(shù)描述
EP20K200CF672C9 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K200CF672I7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K200CF672I8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K200CF672I9 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K200CP208C7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC