參數(shù)資料
型號: EP20K200CF484I8ES
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 84/114頁
文件大?。?/td> 1623K
代理商: EP20K200CF484I8ES
Altera Corporation
71
APEX 20K Programmable Logic Device Family Data Sheet
All specifications are always representative of worst-case supply voltage
and junction temperature conditions. All output-pin-timing specifications
are reported for maximum driver strength.
Figure 36 shows the fMAX timing model for APEX 20K devices.
Figure 36. APEX 20K fMAX Timing Model
Figure 37 shows the fMAX timing model for APEX 20KE devices. These
parameters can be used to estimate fMAX for multipule levels of logic.
Quartus II software timing analysis should be used for more accurate
timing information.
SU
H
CO
LUT
t
ESBRC
ESBWC
ESBWESU
ESBDATASU
ESBADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
PTERMSU
PTERMCO
t
F1—4
F5—20
F20+
LE
ESB
Routing Delay
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