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| 型號： | EP20K160EFI484-3ES |
| 英文描述： | 5V, Byte Alterable E2PROM; Temperature Range: -55°C to 125°C; Package: 36-PGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 46/114頁 |
| 文件大小： | 1623K |
| 代理商： | EP20K160EFI484-3ES |
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Altera Corporation
37
APEX 20K Programmable Logic Device Family Data Sheet
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times of
ESBs. The large capacity of ESBs enables designers to implement complex
functions in one logic level without the routing delays associated with
linked LEs or distributed RAM blocks. Parameterized functions such as
LPM functions can take advantage of the ESB automatically. Further, the
Quartus II software can implement portions of a design with ESBs where
appropriate.
Programmable Speed/Power Control
APEX 20K ESBs offer a high-speed mode that supports very fast operation
on an ESB-by-ESB basis. When high speed is not required, this feature can
be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs
that run at low power incur a nominal timing delay adder. This
Turbo BitTM option is available for ESBs that implement product-term
logic or memory functions. An ESB that is not used will be powered down
so that it does not consume DC current.
Designers can program each ESB in the APEX 20K device for either
high-speed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
I/O Structure
The APEX 20K IOE contains a bidirectional I/O buffer and a register that
can be used either as an input register for external data requiring fast setup
times, or as an output register for data requiring fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. For
fast bidirectional I/O timing, LE registers using local routing can improve
setup times and OE timing. The Quartus II software Compiler uses the
programmable inversion option to invert signals from the row and column
interconnect automatically where appropriate. Because the APEX 20K IOE
offers one output enable per pin, the Quartus II software Compiler can
emulate open-drain operation efficiently.
The APEX 20K IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-core register transfers, or core-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K160EQC208-1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 143 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K160EQC208-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K160EQC208-1X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 143 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K160EQC208-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 143 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K160EQC208-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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