參數(shù)資料
型號(hào): EP20K100RI208-2ES
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 72/114頁
文件大?。?/td> 1623K
代理商: EP20K100RI208-2ES
60
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 24. APEX 20K Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage for internal logic and
input buffers
2.375
(2.375)
2.625
(2.625)
V
VCCIO
Supply voltage for output buffers, 3.3-V
operation
3.00 (3.00)
3.60 (3.60)
V
Supply voltage for output buffers, 2.5-V
operation
2.375
(2.375)
2.625
(2.625)
V
VI
Input voltage
–0.5
4.1
V
VO
Output voltage
0VCCIO
V
T J
Junction temperature
For commercial use
0
85
° C
For industrial use
–40
100
° C
tR
Input rise time (10% to 90%)
40
ns
tF
Input fall time (90% to 10%)
40
ns
Table 25. APEX 20K Device DC Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High-level LVTTL, LVCMOS, or
3.3-V PCI input voltage
1.7, 0.5
× V
CCIO
4.1
V
VIL
Low-level LVTTL, LVCMOS, or
3.3-V PCI input voltage
–0.5
0.8, 0.3
× V
CCIO
V
VOH
3.3-V high-level LVTTL output
voltage
IOH = –12 mA DC,
VCCIO =3.00 V (9)
2.4
V
3.3-V high-level LVCMOS output
voltage
IOH = –0.1 mA DC,
VCCIO =3.00 V (9)
VCCIO – 0.2
V
3.3-V high-level PCI output voltage IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V (9)
0.9
× V
CCIO
V
2.5-V high-level output voltage
IOH = –0.1 mA DC,
VCCIO =2.30 V (9)
2.1
V
IOH = –1 mA DC,
VCCIO =2.30 V (9)
2.0
V
IOH = –2 mA DC,
VCCIO =2.30 V (9)
1.7
V
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