參數(shù)資料
型號: EP20K100RC208-3
英文描述: Advanced 140MHz Triple Video Digitizer with Digital PLL; Temperature Range: -40°C to 85°C; Package: 128-MQFP
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 52/114頁
文件大?。?/td> 1623K
代理商: EP20K100RC208-3
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
相關PDF資料
PDF描述
EP20K100RC208-3ES FPGA
EP20K100RC240-1 8-Bit Video Analog Front End (AFE) with Measurement and Auto-Adjust Features; Temperature Range: 0&degC to 70°C; Package: 80-EPTQFP
EP20K400EFI672-2ES FPGA
EP20K400EFI672-3ES FPGA
EP20K600CF1020I8ES RTC Module With CPU Supervisor
相關代理商/技術參數(shù)
參數(shù)描述
EP20K100RC208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100RC240-1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K100RC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100RC240-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP20K100RC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA