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參數(shù)資料
| 型號(hào)： | EP20K100RC208-1 |
| 英文描述： | High Power LED Driver; Temperature Range: -25°C to 85°C; Package: 20-QFN |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA） |
| 文件頁(yè)數(shù)： | 77/114頁(yè) |
| 文件大小： | 1623K |
| 代理商： | EP20K100RC208-1 |
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Altera Corporation
65
APEX 20K Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
See the Operating Requirements for Altera Devices Data Sheet.
(2)
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5)
All pins, including dedicated inputs, clock I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6)
Typical values are for TA= 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 or 3.3 V.
(7)
These values are specified in the APEX 20K device recommended operating conditions, shown in Table 26 on
page 62.
(8)
The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the
input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown in Figure 33 on page 68.
(9)
The IOH parameter refers to high-level TTL, PCI or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) This value is specified for normal device operation. The value may vary during power-up.
(12) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
(13) Capacitance is sample-tested only.
recommended operating conditions, DC operating conditions, and
capacitance for 1.8-V APEX 20KE devices.
Table 31. APEX 20KE Device Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage
With respect to ground (2)
–0.5
2.5
V
VCCIO
–0.5
4.6
V
VI
DC input voltage
–0.5
4.6
V
IOUT
DC output current, per pin
–25
25
mA
T STG
Storage temperature
No bias
–65
150
° C
T AMB
Ambient temperature
Under bias
–65
135
° C
T J
Junction temperature
PQFP, RQFP, TQFP, and BGA packages,
under bias
135
° C
Ceramic PGA packages, under bias
150
° C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K100RC208-1ES | High Power LED Driver; Temperature Range: -25°C to 85°C; Package: 20-QFN T&R |
| EP20K100RC208-2 | Advanced 170MHz Triple Video Digitizer with Digital PLL; Temperature Range: 0°C to 70°C; Package: 128-MQFP |
| EP20K100RC208-2ES | Advanced 240MHz Triple Video Digitizer with Digital PLL; Temperature Range: 0°C to 70°C; Package: 128-MQFP |
| EP20K100RC208-3 | Advanced 140MHz Triple Video Digitizer with Digital PLL; Temperature Range: -40°C to 85°C; Package: 128-MQFP |
| EP20K100RC208-3ES | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K100RC208-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100RC208-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K100RC208-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100RC208-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K100RC208-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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