鍨嬭櫉(h脿o)锛� | EP20K100FC324-1 |
寤犲晢锛� | Altera |
鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 7/117闋�(y猫) |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC APEX 20K FPGA 100K 208-PQFP |
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Three Reasons to Use FPGA's in Industrial Designs |
妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 84 |
绯诲垪锛� | APEX-20K® |
LAB/CLB鏁�(sh霉)锛� | 416 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 4160 |
RAM 浣嶇附瑷�(j矛)锛� | 53248 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 252 |
闁€鏁�(sh霉)锛� | 263000 |
闆绘簮闆诲锛� | 2.375 V ~ 2.625 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 85°C |
灏佽/澶栨锛� | 324-BGA |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 324-FBGA锛�19x19锛� |
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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APA450-BGG456 | IC FPGA PROASIC+ 450K 456-PBGA |
RMC50DRXS-S734 | CONN EDGECARD 100PS DIP .100 SLD |
GSC65DRYS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
GMC65DRYS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
EPF10K30RI240-4 | IC FLEX 10K FPGA 30K 240-RQFP |
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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EP20K100FC324-1ES | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:FPGA |
EP20K100FC324-1V | 鍔熻兘鎻忚堪:IC APEX 20K FPGA 100K 208-PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:APEX-20K® 鐢�(ch菐n)鍝佽畩鍖栭€氬憡:XC4000(E,L) Discontinuation 01/April/2002 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:XC4000E/X LAB/CLB鏁�(sh霉):100 閭忚集鍏冧欢/鍠厓鏁�(sh霉):238 RAM 浣嶇附瑷�(j矛):3200 杓稿叆/杓稿嚭鏁�(sh霉):80 闁€鏁�(sh霉):3000 闆绘簮闆诲:4.5 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 100°C 灏佽/澶栨:120-BCBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:120-CPGA锛�34.55x34.55锛� |
EP20K100FC324-1X | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 CPLD - APEX 20K 416 Macro 252 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP20K100FC324-2 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪 CPLD - APEX 20K 416 Macro 252 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP20K100FC324-2ES | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:FPGA |