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  • 參數(shù)資料
    型號(hào): EP20K1000EFI1020-1X
    英文描述: FPGA
    中文描述: FPGA的
    文件頁數(shù): 91/114頁
    文件大?。?/td> 1623K
    代理商: EP20K1000EFI1020-1X
    78
    Altera Corporation
    APEX 20K Programmable Logic Device Family Data Sheet
    Note to Table:
    (1)
    These parameters are worst-case values for typical applications. Post-compilation
    timing simulation and timing analysis are required to determine actual worst-case
    performance.
    Tables 42 and 43 describe the APEX 20KE external timing parameters.
    Table 40. APEX 20KE Routing Timing Microparameters
    Symbol
    Parameter
    tF1-4
    Fanout delay using Local Interconnect
    tF5-20
    Fanout delay estimate using MegaLab Interconnect
    tF20+
    Fanout delay estimate using FastTrack Interconnect
    Table 41. APEX 20KE Functional Timing Microparameters
    Symbol
    Parameter
    TCH
    Minimum clock high time from clock pin
    TCL
    Minimum clock low time from clock pin
    TCLRP
    LE clear Pulse Width
    TPREP
    LE preset pulse width
    TESBCH
    Clock high time for ESB
    TESBCL
    Clock low time for ESB
    TESBWP
    Write pulse width
    TESBRP
    Read pulse width
    Table 42. APEX 20KE External Timing Parameters
    Symbol
    Clock Parameter
    Conditions
    tINSU
    Setup time with global clock at IOE input register
    tINH
    Hold time with global clock at IOE input register
    tOUTCO
    Clock-to-output delay with global clock at IOE output register
    C1 = 35 pF
    tINSUPLL
    Setup time with PLL clock at IOE input register
    tINHPLL
    Hold time with PLL clock at IOE input register
    tOUTCOPLL
    Clock-to-output delay with PLL clock at IOE output register
    C1 = 35 pF
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