參數資料
型號: EP20K1000EFC1020-2ES
元件分類: 數字電位計
英文描述: Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 14-TSSOP
中文描述: FPGA的
文件頁數: 41/114頁
文件大?。?/td> 1623K
代理商: EP20K1000EFC1020-2ES
32
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Read/Write Clock Mode
The read/write clock mode contains two clocks. One clock controls all
registers associated with writing: data input, WE, and write address. The
other clock controls all registers associated with reading: read enable
(RE), read address, and data output. The ESB also supports clock enable
and asynchronous clear signals; these signals also control the read and
write registers independently. Read/write clock mode is commonly used
for applications where reads and writes occur at different system
frequencies. Figure 20 shows the ESB in read/write clock mode.
Figure 20. ESB in Read/Write Clock Mode
Notes:
(1)
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2)
APEX 20KE devices have four dedicated clocks.
Dedicated Clocks
2 or 4
4
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
128
× 16
256
× 8
512
× 4
1,024
× 2
2,048
× 1
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
outclken
inclken
inclock
outclock
D
ENA
Q
Write
Pulse
Generator
rden
wren
Dedicated Inputs &
Global Signals
to MegaLAB,
FastTrack &
Local
Interconnect
(2)
相關PDF資料
PDF描述
EP20K1000EFC1020-2X Quad Digital Controlled Potentiometers (XDCP™); Low Noise, Low Power, I2C® Bus, 256 Taps; Temperature Range: -40°C to 85°C; Package: 10-MSOP
EP20K1000EFC1020-3 Quad Digital Controlled Potentiometers (XDCP™); Low Noise, Low Power, I2C® Bus, 256 Taps; Temperature Range: -40°C to 85°C; Package: 10-MSOP
EP20K1000EFC1020-3ES FPGA
EP20K1000EFC672-1ES FPGA
EP20K1000EFC672-2ES FPGA
相關代理商/技術參數
參數描述
EP20K1000EFC1020-2X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1000EFC1020-3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1000EFC1020-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K1000EFC33-1 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K1000EFC33-1X 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256