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參數(shù)資料
| 型號： | EP20K1000EFC1020-1 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 14-TSSOP |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 2/114頁 |
| 文件大?。?/td> | 1623K |
| 代理商： | EP20K1000EFC1020-1 |
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10
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20K devices provide two dedicated clock pins and four dedicated
input pins that drive register control inputs. These signals ensure efficient
distribution of high-speed, low-skew control signals. These signals use
dedicated routing channels to provide short delays and low skews. Four
of the dedicated inputs drive four global signals. These four global signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally generated asynchronous clear signals with high
fan-out. The dedicated clock pins featured on the APEX 20K devices can
also feed logic. The devices also feature ClockLock and ClockBoost clock
management circuitry. APEX 20KE devices provide two additional
dedicated clock pins, for a total of four dedicated clock pins.
MegaLAB Structure
APEX 20K devices are constructed from a series of MegaLABTM
structures. Each MegaLAB structure contains a group of logic array blocks
(LABs), one ESB, and a MegaLAB interconnect, which routes signals
within the MegaLAB structure. The EP20K30E device has 10 LABs,
EP20K60E through EP20K600E devices have 16 LABs, and the
EP20K1000E and EP20K1500E devices have 24 LABs. Signals are routed
between MegaLAB structures and I/O pins via the FastTrack
Interconnect. In addition, edge LABs can be driven by I/O pins through
the local interconnect. Figure 2 shows the MegaLAB structure.
Figure 2. MegaLAB Structure
ESB
MegaLAB Interconnect
Local
Interconnect
To Adjacent
LAB or IOEs
LABs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K1000EFC1020-1ES | Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 14-TSSOP |
| EP20K1000EFC1020-1X | Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 14-TSSOP |
| EP20K1000EFC1020-2 | FPGA |
| EP20K1000EFC1020-2ES | Quad Digitally Controlled Potentiometers (XDCP™); Temperature Range: -40°C to 85°C; Package: 14-TSSOP |
| EP20K1000EFC1020-2X | Quad Digital Controlled Potentiometers (XDCP™); Low Noise, Low Power, I2C® Bus, 256 Taps; Temperature Range: -40°C to 85°C; Package: 10-MSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K1000EFC1020-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K1000EFC1020-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K1000EFC1020-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K1000EFC1020-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K1000EFC1020-2X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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