
4–16
Altera Corporation
Stratix GX Device Handbook, Volume 2
June 2006
SONET Mode Clocking
Figure 4–13. altgxb in SONET Mode With rx_coreclk & tx_coreclk Enabled
For reference, the various input and output clock ports are listed in
Table 4–2. List of Clocking Input & Output Ports Available in SONET Mode
(Part 1 of 2)
Clock
Port
Description
rx_cruclk
Input
Input to CRU available as
a port when CRU is not
trained by the transmitter
PLL.
inclk
Input
Input to the transmitter
PLL, available as a port
when the transmitter PLL
is instantiated.
coreclk_out
Output
Output clock from the
transmitter PLL
equivalent to
TX_PLL_CLK
. Available
as a port if the transmitter
PLL is used.