
6–28
Altera Corporation
Stratix GX Device Handbook, Volume 1
June 2006
Timing Model
Table 6–40. M4K Block Internal Timing Microparameter Descriptions
Symbol
Parameter
tM4KRC
Synchronous read cycle time
tM4KWC
Synchronous write cycle time
tM4KWERESU
Write or read enable setup time before clock
tM4KWEREH
Write or read enable hold time after clock
tM4KBESU
Byte enable setup time before clock
tM4KBEH
Byte enable hold time after clock
tM4KDATAASU
A port data setup time before clock
tM4KDATAAH
A port data hold time after clock
tM4KADDRASU
A port address setup time before clock
tM4KADDRAH
A port address hold time after clock
tM4KDATABSU
B port data setup time before clock
tM4KDATABH
B port data hold time after clock
tM4KADDRBSU
B port address setup time before clock
tM4KADDRBH
B port address hold time after clock
tM4KDATACO1
Clock-to-output delay when using output registers
tM4KDATACO2
Clock-to-output delay without output registers
tM4KCLKHL
Minimum clock high or low time
tM4KCLR
Minimum clear pulse width
Table 6–41. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
Parameter
tMRAMRC
Synchronous read cycle time
tMRAMWC
Synchronous write cycle time
tMRAMWERESU
Write or read enable setup time before clock
tMRAMWEREH
Write or read enable hold time after clock
tMRAMBESU
Byte enable setup time before clock
tMRAMBEH
Byte enable hold time after clock
tMRAMDATAASU
A port data setup time before clock
tMRAMDATAAH
A port data hold time after clock
tMRAMADDRASU
A port address setup time before clock
tMRAMADDRAH
A port address hold time after clock