
Altera Corporation
4–95
February 2005
Stratix GX Device Handbook, Volume 1
Stratix GX Architecture
pin. The I/O standards supported by any particular bank determines
what standards are possible for an external clock output driven by the fast
PLL in that bank.
Table 4–20 shows the I/O standards supported by fast PLL input pins.
Table 4–20. Fast PLL Port Input Pin I/O Standards
I/O Standard
Input
INCLK
PLLENABLE
LVTTL
vv
LVCMOS
vv
2.5 V
v
1.8 V
v
1.5 V
v
3.3-V PCI
3.3-V PCI-X
LVPECL
v
3.3-V PCML
v
LVDS
v
HyperTransport technology
v
Differential HSTL
v
Differential SSTL
3.3-V GTL
v
3.3-V GTL+
v
1.5V HSTL class I
v
1.5V HSTL class II
v
SSTL-18 class I
v
SSTL-18 class II
v
SSTL-2 class I
v
SSTL-2 class II
v
SSTL-3 class I
v
SSTL-3 class II
v
AGP (1
× and 2× )
v
CTT
v