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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1SGX25CF672C6N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 574/1456闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX GX FPGA 25KLE 672FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 20
绯诲垪锛� Stratix® GX
LAB/CLB鏁�(sh霉)锛� 2566
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 25660
RAM 浣嶇附瑷堬細 1944576
杓稿叆/杓稿嚭鏁�(sh霉)锛� 455
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
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Altera Corporation
5鈥�1
February 2005
5. Configuration & Testing
SignalTap
Embedded Logic
Analyzer
Stratix GX devices feature the SignalTap embedded logic analyzer,
which monitors design operation over a period of time through the
IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Stratix GX architecture are
configured with CMOS SRAM elements. Stratix GX devices are
reconfigurable and are 100% tested prior to shipment. As a result, you do
not have to generate test vectors for fault coverage purposes, and can
instead focus on simulation and design verification. In addition, you do
not need to manage inventories of different ASIC designs. Stratix GX
devices can be configured on the board for the specific functionality
required.
Stratix GX devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices that configure Stratix GX devices via a serial data stream.
Stratix GX devices can be configured in under 100 ms using 8-bit parallel
data at 100 MHz. The Stratix GX device鈥檚 optimized interface allows
microprocessors to configure it serially or in parallel, and synchronously
or asynchronously. The interface also enables microprocessors to treat
Stratix GX devices as memory and configure them by writing to a virtual
memory location, making reconfiguration easy. After a Stratix GX device
has been configured, it can be reconfigured in-circuit by resetting the
device and loading new data. Real-time changes can be made during
system operation, enabling innovative reconfigurable computing
applications.
Operating Modes
The Stratix GX architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power up,
SGX51005-1.0
鐩搁棞(gu膩n)PDF璩囨枡
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24AA02T/SN IC EEPROM 2KBIT 400KHZ 8SOIC
EP2AGX95DF25I5 IC ARRIA II GX FPGA 95K 572FBGA
24AA02T-I/SN IC EEPROM 2KBIT 400KHZ 8SOIC
EP2AGX95DF25C4 IC ARRIA II GX FPGA 95K 572FBGA
93C46BX/SN IC EEPROM 1KBIT 2MHZ 8SOIC
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