鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1SGX10DF672C6
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 1036/1456闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX GX FPGA 10KLE 672FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 20
绯诲垪锛� Stratix® GX
LAB/CLB鏁�(sh霉)锛� 1057
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 10570
RAM 浣嶇附瑷堬細 920448
杓稿叆/杓稿嚭鏁�(sh霉)锛� 362
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
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3鈥�2
Altera Corporation
Stratix GX Device Handbook, Volume 1
August 2005
Introduction
multiplication value. The
1 and 2 operation is also possible by
bypassing the SERDES. The SERDES DPA cannot support
1, 2, or 脳4
natively.
On the receiver side, the high-frequency clock generated by the PLL shifts
the serial data through a shift register (also called deserializer). The
parallel data is clocked out to the logic array synchronized with the low-
frequency clock. On the transmitter side, the parallel data from the logic
array is first clocked into a parallel-in, serial-out shift register
synchronized with the low-frequency clock and then transmitted out by
the output buffers.
There are two dedicated fast PLLs each in EP1SGX10 to EP1SGX25
devices, and four in EP1SGX40 devices. These PLLs are used for the
SERDES operations as well as general-purpose use.
Stratix GX Differential I/O Receiver Operation (Non-DPA Mode)
You can configure any of the Stratix GX source synchronous differential
input channels as a receiver channel (see Figure 3鈥�1). The differential
receiver deserializes the incoming high-speed data. The input shift
register continuously clocks the incoming data on the negative transition
of the high-frequency clock generated by the PLL clock (
W).
The data in the serial shift register is shifted into a parallel register by the
RXLOADEN
signal generated by the fast PLL counter circuitry on the third
falling edge of the high-frequency clock. However, you can select which
falling edge of the high frequency clock loads the data into the parallel
register, using the data-realignment circuit.
In normal mode, the enable signal RXLOADEN loads the parallel data into
the next parallel register on the second rising edge of the low-frequency
clock. You can also load data to the parallel register through the
TXLOADEN
signal when using the data-realignment circuit.
Figure 3鈥�1 shows the block diagram of a single SERDES receiver channel.
Figure 3鈥�2 shows the timing relationship between the data and clocks in
Stratix GX devices in
10 mode. W is the low-frequency multiplier and J
is the data parallelization division factor.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
EP20K200EFI484-2X IC APEX 20KE FPGA 200K 484-FBGA
EP20K200EFC484-1X IC APEX 20KE FPGA 200K 484-FBGA
EMC60DRYN-S13 CONN EDGECARD 120POS .100 EXTEND
EMC60DRYH-S13 CONN EDGECARD 120POS .100 EXTEND
RSC30DTEN CONN EDGECARD 60POS .100 EYELET
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