
Altera Corporation
3–9
June 2006
Stratix Device Handbook, Volume 2
External Memory Interfaces in Stratix & Stratix GX Devices
than the clock-to-high-impedance time (tXZ). Stratix and Stratix GX device
I/O pins can interface with ZBT SRAM devices at up to 200 MHz and can
meet ZBT tCO and tSU timing requirements by controlling phase delay in
clocks to the OE or output and input registers using an enhanced PLL.
Figure 3–6 shows a flow-through ZBT SRAM operation where A1 and A3
are read addresses and A2 and A4 are write addresses. For pipelined
ZBT SRAM operation, data is delayed by another clock cycle. Stratix and
Stratix GX devices support up to 200-MHz ZBT SRAM operation using
the 2.5-V or 3.3-V LVTTL I/O standard.
Figure 3–6. tZX & tXZ Timing Diagram
Interface Pins
ZBT SRAM uses one system clock input for all clocking purposes. Only
the rising edge of this clock is used, since ZBT SRAM uses a single data
rate scheme. The data bus, DQ, is bidirectional. There are three control
signals to the ZBT SRAM: RW_N, BW_N, and ADV_LD_N. You can use any
of the Stratix and Stratix GX device user I/O pins to interface to the
ZBT SRAM device.
f
For more information on ZBT SRAM Interfaces in Stratix devices, see
AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX
Devices.
ZBT Bus Sharing
Device tZX
tXZ
tZX
A1
A2
A3
A4
Q(A1)
Q(A3)
D(A3)
clock
addr
dataout
datain
wren