
Altera Corporation
7–49
September 2004
Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
RAM blocks. The 9-bit signed filter coefficients feed directly into the filter
block. As the data is shifted out from the RAM blocks, the multiplexer
block checks for edge pixels and uses the free boundary condition.
Figure 7–28. Block Diagram on Implementation of 3
× 3 Convolutional Filter for an 8 × 8 Pixel Input Image
The 3
× 3 filter block implements the nine multiply-add operations in
parallel using two DSP blocks. One DSP block can implement eight of
these multipliers. The second DSP block implements the ninth multiplier.
The first DSP block is in the four-multipliers adder mode, and the second
is in simple multiplier mode. In addition to the two DSP blocks, an
external adder is required to sum the output of all nine multipliers.