
4–70
Altera Corporation
Stratix Device Handbook, Volume 1
January 2006
Timing Model
1.5-V LVTTL
2 mA
5,460
5,733
ps
4 mA
2,690
2,824
ps
8 mA
1,398
1,468
ps
GTL+
6
ps
CTT
845
887
ps
SSTL-3 Class I
638
670
ps
SSTL-3 Class II
144
151
ps
SSTL-2 Class I
604
634
ps
SSTL-2 Class II
211
221
ps
SSTL-18 Class I
955
1,002
ps
1.5-V HSTL Class I
733
769
ps
1.8-V HSTL Class I
372
390
ps
LVDS
–196
–206
ps
LVPECL
–148
–156
ps
PCML
–147
–155
ps
HyperTransport
technology
–93
–98
ps
(1)
These parameters are only available on row I/O pins.
Table 4–107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins
(Part 1 of 2)
Parameter
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
1,822
1,913
ps
4 mA
684
718
ps
8 mA
233
245
ps
12 mA
111
1
ps
24 mA
–608
–638
ps
Table 4–106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins
(Part 2 of 2)
Parameter
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Min
Max