
Altera Corporation
2–85
July 2005
Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–50 shows the global and regional clocking from the PLL outputs
and the CLK pins.
Figure 2–50. Global & Regional Clock Connections from Side Pins & Fast PLL Outputs Note (1), (2) (1)
PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs.
(2)
The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other PLL must drive
the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Figure 2–51 shows the global and regional clocking from enhanced PLL
outputs and top CLK pins.
2
CLK0
CLK1
CLK2
CLK3
G0
FPLL7CLK
G1
G2
G3
RCLK0
RCLK1
RCLK4
RCLK5
G10
G11
G8
G9
RCLK9
RCLK8
RCLK15
RCLK14
Global
Clocks
Regional
Clocks
PLL 7
l0
l1
g0
PLL 1
PLL 2
FPLL8CLK
PLL 8
2
CLK10
CLK11
CLK8
CLK9
FPLL10CLK
PLL 10
PLL 4
PLL 3
FPLL9CLK
PLL 9
Regional
Clocks
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0